The present invention relates generally to data processing systems and more particularly to an input/output (I/O) controller for a data processing system.
Data processing systems are known wherein an input-output (I/O) bus and a memory bus are each coupled to a central processing unit (CPU). One or more memory devices are coupled to the memory bus and one or more I/O controllers are coupled to the I/O bus. One or more I/O devices are coupled to each I/O controller. A terminal is coupled to the CPU, generally through an RS232 cable. The I/O controllers generally each include an I/O device controller, a buffer RAM, a first direct memory interface (DMA) section for interfacing the I/O device controller to the buffer RAM, a second direct memory interface (DMA) section for interfacing the buffer RAM to the I/O bus and a microprocessor for managing the transfer of data between the I/O device controller and the I/O bus. Usually, each one of the I/O controllers is implemented on a separate printed circuit board. Other data processing systems are known wherein a single bus, referred to as a system bus or a local memory bus, is used instead of an I/O bus and a memory bus combination and the CPU, the memory devices and the I/O controllers are all coupled to the single bus.
The problem with both of these prior art approaches is that they are relatively expensive, are not very practical and take up a relatively large amount of space.
It is an object of this invention to provide a new and improved I/O controller for a data processing system.
It is another object of this invention to provide a data processing system which includes a single I/O controller having a plurality of I/O device controllers for use with a plurality of I/O devices.
It is still another object of this invention to provide an I/O controller for a data processing system for use in interfacing a plurality of I/O devices which includes a plurality of I/O device controllers, a single buffer RAM which is shared by all of the I/O device controllers and a single microprocessor which manages the transfer of data between the plurality of I/O device controllers and the buffer RAM.
It is a further object of this invention to provide a gate array construction for implementing the logic in a plurality of direct memory access interface sections for a plurality of I/O device controllers.